CODEWITHSUNDEEP
vhdl
Gaurav Prasad
Gaurav Prasad

Reputation: 61

VHDL mux 8:1 error in test bench

it is 8x1mux vhdl program main program working with no error, but in test their is some signal i,s ,y are shows error and tell i,s,y are already declared.

test bench

error in test bench

enter image description here

Upvotes: 0

Views: 3655

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

The code says:

...
entity mux8x1_t is
end mux8x1_t;

architecture mux8x1_t_a of mux8x1 is
  component mux8x1
...

So the architecture is not for the just declared entity as is probably the intention, another architecture for the mux8x1, and since the mux8x1 has ports named i, s, and y, the signals named i, s, and y in the architecture make the compile generate the error.

The architecture part should be changed to:

architecture mux8x1_t_a of mux8x1_t is

For the error near "=": syntax error, change ;= to :=.

Upvotes: 3

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