CODEWITHSUNDEEP
verilogmuxtest-bench
Roman Andreevitch Biriukov
Roman Andreevitch Biriukov

Reputation: 65

Why does 4-bit mux test bench code give x?

I can't put my finger on why is it not working. I ran a simulation on edaplayground, and I get an "x" in the output every time the select changes to 0. I properly get "1" when sel is "1" though.

The code: 

 module mux8_2(input [3:0]a,[3:0]b,sel,output [3:0]out);   
 assign out=(sel)?a:b;  
 endmodule

and the testbench:

 module mux8_2_tb; 

 reg [3:0]A;  

 reg [3:0]B;  

 reg SEL;  

 wire [3:0]OUT;  

 mux8_2 UUT(A,B,SEL,OUT);  

 initial  
  begin  

 $dumpfile("dump.vcd");  

 $dumpvars(1);  

 A=4'b1; B=4'b0; SEL=1'b1;

 #1 SEL=1'b0;  
 #1 SEL=1'b1;  
 #1 SEL=1'b0;  
 #1 SEL=1'b1;  
 #1 SEL=1'b0;  
 #1 SEL=1'b1;  
 #1;
 end

 endmodule

Upvotes: 1

Views: 1518

Answers (1)

toolic
toolic

Reputation: 62037

I can't reproduce your results; the OUT signal is always known for me.

But, I do get a compile warning: 

The following 1-bit expression is connected to 4-bit port "sel" of module 
  "mux8_2", instance "UUT"

This can be fixed:

module mux8_2(input [3:0]a,[3:0]b, input sel,output [3:0]out);

In your code sel inherited the width from the previous signal ([3:0]b). Your code is equivalent to:

module mux8_2(input [3:0]a,[3:0]b,[3:0]sel,output [3:0]out);

Adding another input keyword before sel forces it to use the default width of 1 bit.

Upvotes: 1

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