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vectorvhdltest-bench
F_Schmidt
F_Schmidt

Reputation: 1132

How can I test all cases of vector multiplexer in VHDL?

This is my first VHDL code, I have this multiplexer (two inputs, one selection bit) which has 8bit-vector inputs. How can I write a testing function that generates all possible vectors? 

library IEEE;
use IEEE.std_logic_1164.all;

entity mux is
port(
    in0, in1: in std_logic_vector(7 downto 0);
    sel: in std_logic;
    out0: out std_logic_vector(7 downto 0);
end mux;

architecture dataflow of mux is
begin
    out0<=in1 when sel='1'
    else in0;
end dataflow;

This is the testbench at the moment:

library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is --empty
end testbench;

architecture tb of testbench is

-- DuT component
component mux is
port(
    in0, in1: in std_logic_vector(7 downto 0); 
sel: in std_logic;
    out0: out std_logic);
end component;

signal tb_sel: std_logic;
signal tb_in0, tb_in1, tb_out0: std_logic_vector(7 downto 0);

begin
-- Connect DuT
DuT: mux port map(tb_in0, tb_in1, tb_sel, tb_out0);

process
begin
    tb_sel <= 0;
    tb_in0 <= "00000000";
    tb_in1 <= "00000000";

    -- TODO: test all possibilities


    end process;
end tb;

Upvotes: 0

Views: 730

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15924

Something like this can be used:

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench is --empty
end testbench;

architecture tb of testbench is

signal tb_sel: std_logic;
signal tb_in0, tb_in1, tb_out0: std_logic_vector(7 downto 0);

begin
-- Connect DuT

  DuT: entity work.mux port map(tb_in0, tb_in1, tb_sel, tb_out0);

process
begin
    -- Done: Test all possibilities

    for sel in 0 to 1 loop
      for in0 in 0 to 2 ** tb_in0'length - 1 loop
        for in1 in 0 to 2 ** tb_in1'length - 1 loop
          -- Make stimuli
          if sel = 0 then
            tb_sel <= '0';
          else
            tb_sel <= '1';
          end if;
          tb_in0 <= std_logic_vector(to_unsigned(in0, tb_in0'length));
          tb_in1 <= std_logic_vector(to_unsigned(in1, tb_in1'length));
          -- Wait for output, also to ease viewing in waveforms
          wait for 10 ns;
          -- Test output
          if sel = 0 then
            assert tb_out0 = tb_in0 report "Wrong out0 output value for selected in0 input" severity error;
          else
            assert tb_out0 = tb_in1 report "Wrong out0 output value for selected in1 input" severity error;
          end if;
        end loop;
      end loop;
    end loop;

    report "OK   (not actual failure)" severity FAILURE;
    wait;

    end process;
end tb;

Note that I have used instantiation by entity for mux, to avoid the component declaration, where there actually was an error in the port list; clearly showing why it is a bad idea to write the same twice ;-)

Also not that I have included the IEEE numeric_std package.

It can surely be improved with respect to testing of X values also, but for a simple module like a mux the testing above will give the required coverage.

For more advanced testing, take a look at OSVVM.

Upvotes: 2

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