CODEWITHSUNDEEP
vhdlmultiplexing
Jonathan D
Jonathan D

Reputation: 19

VHDL mux implementation?

Is it possible to implement a mux with multiple control signals? For example, I want to do something like this:

with (sig1 & sig2) select  
output <= A when "00",  
B when "01",  
C when "10",  
D when "11",  
'0' when others;

I know I could just assign them to a new signal and use that, but that's something I want to avoid if possible.

Upvotes: 1

Views: 4338

Answers (2)

Martin Thompson
Martin Thompson

Reputation: 16802

You need to enable VHDL2008 mode on your compiler to have it work.

An alternative (also 2008):

muxing: process (sig1, sig2) is
begin  -- process muxing
    case sig1 & sig2 is
        when "00" => output <= '1';
        when "01" => output <= '0';
        when "10" => output <= '0';
        when "11" => output <= '1';
        when others => output <= '0';
    end case;
end process muxing;

If you have no VHDL-2008 mode on your compiler it will fail with complaints of

Array type case expression must be of a locally static subtype.

or similar.

If your compiler can't be made to be VHDL-2008 compliant, you have to work around this by creating a type that you can use to surround the sig1 & sig2 to explicitly tell the compiler what's going on:

subtype twobits is bit_vector(0 to 1);

Then:

with twobits'(sig1 & sig2) select  
    output <= '1' when "00",  
    -- etc.

or:

case twobits'(sig1 & sig2) is
     when "00" =>  -- etc.

Upvotes: 3

edgarmtze
edgarmtze

Reputation: 25048

See this, maybe it helps you

entity MUX is
  port ( a, i0, i1 : in bit;
         o : out bit );
end MUX;

architecture behave of MUX is
begin
  process ( a, i0, i1 ) begin
    if  a = '1'  then
      o <= i1;
    else
      o <= i0;
    end if;
end process;
end behave;

Upvotes: 1

Related Questions