Reputation: 1
i try to do in EDA playground platform a code for 8x1 multiplexer put something is going wrong. The show me an error that i search it and i found that is from verilog language and i don't understand why? i check again and again my code and i dont find any mistake. please see the code from the link below to run it and help me to solve is problem and i understand why is apear me that error
https://www.edaplayground.com/x/2T3x
Upvotes: 0
Views: 4507
Reputation: 1
Thanks for the help. My code is now working
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
--declaration for 8x1
entity mux8x1 is
port( I : in std_logic_vector(7 downto 0); -- input that need 8x1
s: in std_logic_vector(2 downto 0); --is the enable
Y: out std_logic -- output of 8x1 is the output
);
end mux8x1;
architecture behavioral of mux8x1 is
signal f0,f1,f2,f3 : std_logic;
begin
process(I,S)
begin
if s(0)='0' then
f0<=I(7);
f1<=I(5);
f2<=I(3);
f3<=I(1);
else
f0<=I(6);
f1<=I(4);
f2<=I(2);
f3<=I(0);
end if;
if (s(1)='0' and s(0)='0')then
Y<=f0;
if (s(1)='0' and s(0)='1')then
Y<=f1;
if (s(1)='1' and s(0)='0')then
Y<=f2;
if (s(1)='1' and s(0)='1')then
Y<=f3;
end if;
end if;
end if;
end if;
end process;
end behavioral;
Upvotes: 0
Reputation: 1424
you need to rename your testbench to something different to your module.
Call it 'multiplexer_test
' instead.
i.e. the following lines
testbench.vhd
ENTITY multiplexer IS
END multiplexer;
ARCHITECTURE behavior OF multiplexer IS
to
ENTITY multiplexer_test IS
END multiplexer_test;
ARCHITECTURE behavior OF multiplexer_test IS
And also you need to change the top entity to multiplexer_test
instead of testbench
i.e.
Or if you just rename the testbench module from multiplexer
to testbench
then you don't need to do the second step
Upvotes: 1