Reputation: 2486
I need to create XOR with 4:1 Mux (I know that it's easier without a Mux...)
I found this useful example for 4:1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity multiplexer4_1 is
port (
i0 : in std_logic;
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
sel : in std_logic_vector(1 downto 0);
bitout : out std_logic
);
end multiplexer4_1;
architecture Behavioral of multiplexer4_1 is
begin
process(i0,i1,i2,i3,sel)
begin
case sel is
when "00" => bitout <= i0;
when "01" => bitout <= i1;
when "10" => bitout <= i2;
when others => bitout <= i3;
end case;
end process;
end Behavioral;
But I'm somehow confused how to tell the mux to output 1 when 01 or 10 is the input and 0 otherwise. Can I assign values to i0-i3? Sorry I'm new to VHDL
Upvotes: 1
Views: 5250
Reputation: 16832
Your MUX connects one input to the output based on the select signals.
If you imagine the select signals are the "inputs" to your XOR gate, you just need to figure out what the output should be for each combination of the XOR inputs (the select signals). Then wire up the MUX inputs such that the right level comes out for each select input.
The VHDL syntax for that is just
inst: entity work.multiplexer4_1
port map
(
i0 => '1'; -- or '0'
etc..
sel => xor_input_signals;
bitout => xor_output_signal
);
Upvotes: 1
Reputation: 185
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor4_1 is
port (
--i0 : in std_logic;
--i1 : in std_logic;
--i2 : in std_logic;
--i3 : in std_logic;
sel : in std_logic_vector(1 downto 0);
bitout : out std_logic
);
end xor4_1;
architecture Behavioral of xor4_1 is
signal i0 : std_logic;
signal i1 : std_logic;
signal i2 : std_logic;
signal i3 : std_logic;
begin
process(i0,i1,i2,i3,sel)
begin
case sel is
when "00" => bitout <= i0;
when "01" => bitout <= i1;
when "10" => bitout <= i2;
when others => bitout <= i3;
end case;
end process;
-- Now just hardcode the input bits to the appropriate values.
-- I might be mistaken, but I'm pretty sure this is how the implementation tool
--s actually would implement an XOR gates.
i0 <= '0';
i1 <= '1';
i2 <= '1';
i3 <= '0';
end Behavioral;
Upvotes: 1
Reputation: 1145
I'm assuming you have to build an XOR gate with 2 inputs. One possibility would be to connect the two inputs to sel(0)
and sel(1)
respectively. You can then connect constant values to your remaining inputs i0
to i3
such that the truth table of your MUX4 is the same as for an XOR gate.
Upvotes: 1