CODEWITHSUNDEEP
vhdl
D.Wei
D.Wei

Reputation: 55

How to implement xor gate which has n bits input, 1 bit output in the VHDL

As title, The code of entity like :

entity n_in_1_out_xor_gate is
    generic(
       bits                 : integer
    );
    port (
        n_in                : in  std_logic(bits-1 downto 0);
        xor_gate_out        : out std_logic
    ); 
end n_in_1_out_xor_gate;

How to implement body of code? Does anybody help me? Thanks!

Upvotes: 1

Views: 1291

Answers (1)

Tricky
Tricky

Reputation: 4461

With vhdl 2008, you can simply write:

xor_gate_out <= xor n_in;

if you're stuck with vhdl '93, all compilers I have ever used support the std_logic_misc non-standard library that contain reduction functions:

xor_gate_out <= xor_reduce(n_in);

Upvotes: 4

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