CODEWITHSUNDEEP
vhdl
NRagot
NRagot

Reputation: 294

how to make a fully generic MUX in VHDL 93

I would like to synthesis a generic MUX with two generics :

This seems fairly easy as per these very similar question : 3459057 and 32562488. The catch is : I must use vhdl 93, and both the answer assumes vhdl 2008 and/or only one of the generics to be a given.

entity Mux is
    generic (
        addressSize : integer := 2;
        wordSize    : integer := 32
    );
    port (
        …
    );
end entity;

architecture RTL of Mux is
begin
…
end architecture;

I'm stuck, Indeed, in vhdl 93, I may not use unconstrained std_logic_vector in array:

package common is
    type WORD_ARRAY_type is array (integer range <>) of std_logic_vector;
end package;

Which would have let me use both generics has such :

port(
   input : WORD_ARRAY_type(0 to addressSize)(wordSize - 1 downto 0);
   …
);

and, of course, I may not define a type in between the generics and ports. The thing is, I must certainly not be the first person who encounters this specific question so I wander : "How would one do this very classic function in VHDL 93 ?"

Upvotes: 0

Views: 524

Answers (1)

Jim Lewis
Jim Lewis

Reputation: 3973

I understand what you think you want, however, for a small combinational logic block like this, I would use a function instead and then use overloading to define the a Mux function for each Mux size you need:

function Mux (
    sel  : std_logic ;
    A1   : std_logic_vector ;
    A2   : std_logic_vector 
) return std_logic_vector is 
  variable Y : std_logic_vector(A1'range) ; 
begin
  case sel is 
    when '0' => Y := A1 ; 
    when '1' => Y := A2 ;
    when others => Y := (others => 'X') ; 
  end case ; 
  return Y ; 
end function Mux ;

Yes it is brute force to develop the package, but once done, it is very simple to use. Reference the package and do the function call. And since it is a function, you can chain the outputs together.

MuxOut <= Mux(Sel, A, B) and Mux(Sel, C, D) ;

If you would like to see something like this in the IEEE standard (which would be a good idea), reach out to me and I can help you get started in participating.

Above, I enforced the sizing to be the same by using the variable. VHDL-2019 gives us better options. In fact, it gives us ways to allow the types of A1, ... to be more flexible than just std_logic_vector.

Adding on the @Tricky method, but applying it to subprograms:

function Mux (
    Width : integer ; 
    sel   : integer ;
    A     : std_logic_vector 
) return std_logic_vector is 
  alias normalizedA : std_logic_vector(0 to A'length-1) is A ; 
  constant WordStart : integer := width * sel ; 
begin
  return normalizedA(WordStart to WordStart + Width - 1) ; 
end function Mux ;

Upvotes: 1

Related Questions