Reputation: 11
I wrote this entity but i don't know how to write the architecture.It has to be done by using generics and it needs to work for any DMUX (1:2,1:4,1:8,1:16 etc) if I change the Nr_sel (number of selection inputs). The data(input) is on 1 bit.
entity DMUX is
generic (
Nr_sel: integer:= 3
);
port (
Input: in std_logic;
Sel: in std_logic_vector (Nr_sel - 1 downto 0);
Outputs: out std_logic_vector(2**Nr_sel - 1 downto 0)
);
end DMUX;
Upvotes: 0
Views: 583
Reputation: 4041
It could be achieved the following way:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity DMUX is
Generic (
num_sel : positive := 1 -- or 2, 3, ... etc.
);
Port (
SEL : in unsigned(num_sel - 1 downto 0);
DIN : in std_logic;
DOUT : out std_logic_vector(2**num_sel - 1 downto 0)
);
end entity DMUX;
architecture Behavioral of DMUX is
begin
output_p : process (
SEL,
DIN
)
begin
-- default assignment
DOUT <= (others => '0');
DOUT(to_integer(SEL)) <= DIN;
end process output_p;
end architecture Behavioral;
Depending on your needs, you could also have low-active logic, i.e. all ones (others => '1') and invert DIN.
Upvotes: 1
Reputation: 18299
I believe the right method would be to use generate
, since we have a variable number of outputs, while all of them have to be assigned, and without any sequential logic:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity DMUX is
generic (
Nr_sel: integer:= 3
);
port (
Input: in std_logic;
Sel: in std_logic_vector (Nr_sel - 1 downto 0);
Outputs: out std_logic_vector(2**Nr_sel - 1 downto 0)
);
end DMUX;
architecture Arch of DMUX is
begin
GEN_OUT:
for i in 0 to (2**Nr_sel - 1) generate
Outputs(i) <= Input when (to_integer(Sel) = i) else '0';
end generate GEN_OUT;
end Arch;
I haven't tested it's functionality, but it compiles and gives the idea.
Upvotes: 0