CODEWITHSUNDEEP
genericsvhdl
Wile E Coyote
Wile E Coyote

Reputation: 71

Is it possible to code a generic DEMUX (1 input, multiple outputs) in VHDL?

My FPGA software has a drag and drop feature to developing elements or system design. It works best with "generic" components that allows the user to set the modifiable parameters without having to go into the code and change things. To that end I decided to create a generic demuxer with one input and multiple outputs. The design must allow the user to define the number of outputs and the bitwidth of the input and output ports (both are same width). The design also has to determine the bitwidth of the output select port depending upon the number of output ports selected (that part I have taken care of with a function). Please note that due to my limitations the number of output ports can be between 2 and 256 outputs. Is it possible to code for variable number of outputs in a design or is it a pipe dream. Please note that I have written code for many fixed output demuxes.

Upvotes: 1

Views: 1200

Answers (2)

Wile E Coyote
Wile E Coyote

Reputation: 71

To A.K and scary_jeff, thanks for the response. I will check with my tool to see if it is compliant with VHDL-2008. Just so you know, I am very new to VHDL and learning quickly but it doesn't take long for me to get into more complicated designs that I end up trying to make as simple as possible. The are a couple of lines that I sort of follow but are new to me such as;

output : OUT demux_output(0 TO NB_OUTPUT - 1)(PORT_WIDTH - 1 DOWNTO 0);

While I understand what it is saying, in all of the research I have done none of it showed a capability or an example like it. The other line;

output <= (OTHERS => (OTHERS => '0'));

Again I have never seen any documentation on the keyword "others" so the line doesn't make sense to me. Can you explain or maybe let me know of a "good" VHDL resource I can use. That way instead of asking newbie type questions I can ask for help on more complex issues. Again, thanks.

Upvotes: 0

A. Kieffer
A. Kieffer

Reputation: 372

I'm not sure I perfectly understood what you were looking for, but I'll try to answer correctly.

First of all it depends if your tool support VHDL-2008 or not. Many customizable features are unavailable in VHDL-1993.

If you do this can probably work:

You first need to define a type in a package your_package.vhdl

TYPE    demux_output    IS ARRAY (natural range <>) OF  std_logic_vector;

Then you can define your entity as follow :

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE WORK.your_package.ALL;

ENTITY demux IS
    GENERIC (PORT_WIDTH : integer := 8; -- define your data width
            NB_OUTPUT : integer := 50); -- define the number of outputs needed

    PORT    (input      : IN std_logic_vector(PORT_WIDTH - 1 DOWNTO 0);
            output      : OUT demux_output(0 TO NB_OUTPUT - 1)(PORT_WIDTH - 1 DOWNTO 0);
            sel         : IN std_logic_vector(7 DOWNTO 0));

END ENTITY;

ARCHITECTURE RTL OF demux IS

SIGNAL sel_int  : integer := 0;

BEGIN

sel_int <= to_integer(unsigned(sel));

PROCESS (sel_int, input)
BEGIN
    output <= (OTHERS => (OTHERS => '0'));
    FOR i IN 0 TO (NB_OUTPUT - 1) LOOP
        IF (i = sel_int) THEN
            output(i) <= input;
        END IF;
    END LOOP;
END PROCESS;

END ARCHITECTURE;

There, you only need to declare the width of your ports (PORT_WIDTH) and the number of output ports (NB_OUTPUT).

If your tool isn't compliant with VHDL-2008 you won't be able to declare an unconstrained data width in the type demux_output. That's why you'll have to define a global constant, but this would probably lose the "customizable part" that you're looking for.

Upvotes: 1

Related Questions