CODEWITHSUNDEEP
pythonverilogsystem-verilogpygears
Sreda
Sreda

Reputation: 58

PyGears hdlgen generates top level module with DTI interfaces, Vivado is expecting Verilog which does not support this feature

I made my module whish looks like this

from pygears import gear
from pygears.typing import Fixp, Tuple
from pygears.lib import add, qround, saturate, drv, collect
from pygears.sim import sim
from pygears.hdl import hdlgen

@gear
def adder(data: Tuple[Fixp[10, 32], Fixp[10, 32]]):
  return add(data[0],data[1]) \
    | qround (fract=21) \
    | saturate(t=Fixp[11, 32])
    
hdlgen('/adder',outdir='./Example1/adder_hdl',copy_files='True')

Now, my top level module interfaces are DTI interfaces

module adder(
    input logic clk,
    input logic rst,

    dti.consumer data, // (q10.22, q10.22) (64)
    dti.producer dout // q11.21 (32)

);

Since Vivado is expecting top level wrapper to be in Verilog is there any way to tell PyGears to convert top level interfaces into standard ports?

Upvotes: 2

Views: 115

Answers (1)

Francin
Francin

Reputation: 321

Yes, there is a way.

Use parameter toplang for hdlgen function and set it to 'v' for Verilog. Something like this

hdlgen('/adder',outdir='./Example1/adder_hdl',copy_files='True',toplang='v')

This will produce top wrepper called adder_v_wrap and interface will have Verilog ports

module adder_v_wrap
(
    input clk,
    input rst,

    output reg  data_ready,
    input  wire data_valid,
    input  wire [63:0] data_data,
    input  wire         dout_ready,
    output reg          dout_valid,
    output wire  [31:0] dout_data

);

Upvotes: 4

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