CODEWITHSUNDEEP
vhdlunsigned
harry
harry

Reputation: 47

How to truncate 16 bits to 8 bits VHDL?

Hi I have the following code

 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 entity mult is 
 PORT (in1, in2 : IN UNSIGNED (7 downto 0);
 product: OUT UNSIGNED (7 downto 0));
 end mult;
 Architecture behaviour of mult is 
 signal prod_sig: UNSIGNED (7 downto 0);
 begin

 product<=in1*in2; --this cause an error because it needs to be truncated to its 8 bit equivalent 

 end behaviour;

Can someone help me understand how to truncate the product please

Upvotes: 0

Views: 1881

Answers (1)

Owen
Owen

Reputation: 39356

In VHDL, you work directly with bits, so there is no notion of "truncate" as in C.

Rather, just select the bits you want:

signal full_product: UNSIGNED (15 downto 0);

...

full_product <= in1 * in2;
product <= full_product (7 downto 0);

Upvotes: 1

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