CODEWITHSUNDEEP
vhdl
BlueAngel45
BlueAngel45

Reputation: 31

How to Sign Extend a 4bit vector to 16bit vector in VHDL?

I'm new to VHDL and I'm wondering how to use sign extension on a 4bit number to extend it to a 16bit number. I understand the idea of sign extension and how it works, but I'm having a hard time trying to find a way to implement it in my VHDL assignment. I have a small start but am wondering where to go from here.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Entity Signextend is
    port(
        numIn       :   in  std_logic_vector( 3 downto 0);
        numOut      :   out std_logic_vector(15 downto 0)
        );
End Signextend;

architecture signex of Signextend is

begin

    numOut(3)   <=  numIn(3);
    numOut(2)   <=  numIn(2);
    numOut(1)   <=  numIn(1);
    numOut(0)   <=  numIn(0);
--Trying to add the rest of the vectors, not sure how to proceed.

end signex;

This might not even be the correct start, but could someone point me in the right direction? Or show me how to pad the number with 0s or 1s depending on the sign of the number? Thanks for the help!

Upvotes: 2

Views: 7259

Answers (2)

K.Khallaf
K.Khallaf

Reputation: 47

You can simply concatenate zeros to the input vector if it is a positive number or ones if it is a negative number and then assign the value to your output vector

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SignExtend is
        Port (
                Input: in STD_LOGIC_VECTOR(4 downto 0);
                Output: out STD_LOGIC_VECTOR(31 downto 0)
              );
end SignExtend;

architecture Behavioral of SignExtend is
begin
process(Input)
begin
if (Input(4)='1') then --Checking if the first bit of the input bits is '1'
Output<="111111111111111111111111111"&Input; --The input is a negative number
else --The input is a positive number
Output<="000000000000000000000000000"&Input;
end if;
end process;
end Behavioral;

Upvotes: 1

Tricky
Tricky

Reputation: 4516

This functionality is provided for you in the numeric_std package. When you use type signed from this library, the resize function will sign extend for you.

for example:

use ieee.numeric_std.all;

signal signed_8bit : signed(7 downto 0);
signal signed_16bit : signed(15 downto 0);

....

signed_16bit <= resize(signed_8bit, signed_16_bit'length);

Sign extension means little with std_logic_vector as this type is not meant to represent numerical values.

Upvotes: 3

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