CODEWITHSUNDEEP
vhdl
michalmonday
michalmonday

Reputation: 502

VHDL initial value is reset

Declared initial value of signal is reset to 0 when a process is added (to my understanding that process shouldn't affect it).

Signal declaration:

signal current_level_index : integer range 0 to 7 := 6;

Process that causes the current_level_index initial value to be set to 0.

process (i_increase_level_clk) -- this clk is provided from a switch/button I have to physically press
    begin
-- deleting 3 lines below solves the problem
        if rising_edge(i_increase_level_clk) then
            current_level_index <= current_level_index + 1;
        end if;
end process;

Do you know what could be the reason for it?

I am not able to simulate this code, I compiled it with IceCube2 for the "Nandland Go Board (iCE40 HX1K VQ100 3.3V)" and observed the results on a display.

Here's the whole file: https://github.com/michalmonday/files/blob/master/vhdl_issue/game_logic.vhd

Here's whole project: https://github.com/michalmonday/files/tree/master/vhdl_issue

The same code/file has the same issue in another place:

    type level is record 
        pos : integer range -3 to 8;
        length : integer range 1 to 3;
    end record;

    type level_array is array (0 to 7) of level;

    signal levels : level_array := (
        -- pos, length
        (4,1),
        (4,1),
        (4,1),
        (4,2),
        (4,2),
        (3,3),
        (3,3),
        (3,3));

The "pos" of all levels is also set to 0 (it shouldn't be, it should be either 3 or 4). The "length" of all levels has always correct value.

Here's the part (process) of the code that affects position of levels:

    process (game_clk)      
        variable reverse_dir : std_logic := '0';
    begin
        if rising_edge(game_clk) then
            if levels(current_level_index).pos > 7 then
                reverse_dir := '1';
            elsif levels(current_level_index).pos < 1-levels(current_level_index).length then
                reverse_dir := '0';
            end if;

            if reverse_dir = '0' then
                levels(current_level_index).pos <= levels(current_level_index).pos + 1;
            else 
                levels(current_level_index).pos <= levels(current_level_index).pos - 1;
            end if;
        end if;
    end process;

Edit: I think this may be the answer: https://stackoverflow.com/a/23798653/4620679

Upvotes: 1

Views: 1120

Answers (1)

michalmonday
michalmonday

Reputation: 502

From "VHDL for Engineers" (p. 87, about ":=" operator) by Kenneth L. Short:

"Initial signal values are useful for simulation, but not for synthesis. For synthesis, any initial or default value assigned to a signal is ignored by an IEEE 1076.6 compliant synthesizer. This is because the synthesizer cannot assume that the target hardware has the capability to be powered up with its signals in the specified states. Note that there are some synthesizers that attempt to synthesize initial values (with varying degrees of success). However, for a design description to be IEEE Std1076.6 compliant, initial values must not be assigned to signals or variables."

Upvotes: 1

Related Questions