CODEWITHSUNDEEP
verilog
Lakshmi j.l
Lakshmi j.l

Reputation: 13

Reading data from ROM

I want to read data from ROM at each clock cycle. I have the program for ROM as below

`timescale 1ns / 1ps 
module ROM (clk,rd,addr,data);

input wire  [5:0]addr;
output reg[1:0] data;
reg[1:0] rom [0:39];
input wire rd,clk;

 initial begin 

$readmemb ("own1.mem",rom);

end
always @(posedge clk) begin
data <=  rom[addr];
end
endmodule

The addr is not incrementing, so that I need to read one data each time. How do I do that? I have attached the simulation result.

can the clock process can be modified as

always @(posedge clk)
count =addr;
assign count_next =count +1;
counter <=count_next;
data <= rom[counter];

will this work?? to increment address and access data at each clock edge??

Testbench

module tb_ROM;

    // Inputs
    reg clk;
    reg rd;
    reg [5:0] addr;
    wire [5:0] temp,counter;
    // Outputs
    wire [1:0] data;

    // Instantiate the Unit Under Test (UUT)
    ROM uut (
        .clk(clk), 
        .rd(rd), 
        .addr(addr), 
        .data(data)
    );

    initial begin
        // Initialize Inputs
        clk = 1;
        rd = 1;
    
      addr=0;
        // Wait 100 ns for global reset to finish
    
        // Add stimulus here

    end
     always #5 clk=~clk; 
      
endmodule

ROM simulation

Upvotes: 1

Views: 1174

Answers (1)

toolic
toolic

Reputation: 62236

In your testbench, you can add another always block to increment the address:

always @(posedge clk) addr <= addr + 1;

Or, that can be added in the design module instead, if that is the goal.

Upvotes: 1

Related Questions