CODEWITHSUNDEEP
verilogbit-shiftbit
john_log
john_log

Reputation: 13

Reading data in verilog

Problem: I'm trying to manipulate 16 bit binary numbers in Verilog. The results I'm getting do not seem to match the expected results. I've isolated the problem in that the testbench.v seems to be sending the wrong values to my classify.v file.

This is what my testbench.v file looks like.

module testbench3();

reg clk, reset; // clock and reset are internal
reg [0:15] data_row;
wire [0:1] actual_class;
reg EN;
reg [0:15] memory [0:2]; //HERE
integer i;

classify dut(.actual_class(actual_class), .data_row(data_row), .EN(EN));

// Set up the system clk
always begin
    #5 clk <= !clk;
end

initial begin     // ASSIGN 16 bit to memory
  memory[0] <= 0001111111000000;
  memory[1] <= 0010111111000000;
  memory[2] <= 0010111111000000;

end

initial begin
    clk <= 0;

    EN <= 0;
    i <= 0;
    reset <= 0; 
    #27; 
    reset <= 1;
end

always @(posedge clk) begin 
    data_row <= memory[i];
    i <= i + 1;
    $display ("%b", data_row); // HERE
    if(i == 3) begin
        $display("End simulation");
        $finish;
    end
  EN = 1;
end

endmodule

I'm expecting the console to display:

  1. 0001111111000000
  2. 0010111111000000
  3. 0010111111000000

and what I'm getting are these values instead:

  1. 0101111111000000
  2. 1110111111000000
  3. 1110111111000000

Not sure where these values are coming from.

I'm using Icarus Verilog 0.10.0, if that helps.

Upvotes: 1

Views: 435

Answers (1)

Oldfart
Oldfart

Reputation: 6259

When you initialize your memory your are using decimal values, not binary. Add 16'b to the front:

memory[0] <= 16'b0001111111000000;
memory[1] <= 16'b0010111111000000;
memory[2] <= 16'b0010111111000000;

Upvotes: 1

Related Questions