CODEWITHSUNDEEP
assemblymipsinstruction-encoding
Js Park
Js Park

Reputation: 1

Why is multiplication by 4 needed to offset when you calculate branch target address?

I understand when I translate C code into MIPS language, the address needs to be multiplied by 4. i.e ) int x = A[1] => lw $t1, 4*1 (address of A)

But I don't know why it is also the case for branch target address.

From this Q&A How to Calculate Jump Target Address and Branch Target Address?
I read that offset needs to be word-aligned since PC address is so. But then, isn't the offset address needed to be divided by 4, since PC is word-aligned, and offset address is byte-aligned ?

I think I have some misconception here.

Upvotes: 0

Views: 1788

Answers (1)

Erik Eidt
Erik Eidt

Reputation: 26646

MIPS instruction are all 4 bytes long — and they are always located on even word boundaries.  As such, this applies to all instruction addresses — branch source as well as branch target — and hence all branch offsets have the low 2 bits as being 0, because they are the difference between two word-aligned instruction addresses.

It would be wasteful to encode those always 0 bits in the instruction, so they are omitted.

Rather than encoding bits known to always be zero into the instruction field, those 2 bits are repurposed to allow for a larger branch displacement immediate.  This is why there is a /4 or *4 depending on whether encoding or decoding.

(In fact, the PC register will always hold zeros for the low two bits, so the hardware doesn't even need a 32 bit register for the PC, a 30 bit register would suffice, and +1 instead of +4 to increment — if it was me that's how I'd try to setup the hardware internally.)

Upvotes: 2

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