CODEWITHSUNDEEP
compiler-errorsverilogsystem-verilogdivision
Silence
Silence

Reputation: 395

Division using 4-bit Full Adder and Calling the module whenever it is required

I'm trying to build ALU.
I built a 4-bit Full Adder and a 4-bit Full Subtractor using Half Adder and Half Subtractor respectively.

module fullAdder4bit(output [3:0] sum, output c_out, input [3:0] a, b, input  c_in);
    wire [2:0] c;
    fullAdder FA1(sum[0], c[0], a[0], b[0], c_in);
      ----
      ----
      ----
      ----
endmodule

And, similarly, I wrote for Full Subtractor.

Using these, I was trying to build a Division, but I'm not getting exactly how to write Division using the above Full Adder. If anyone knows how to write for Division, let me know.


When the user gives A+B or A-B, it should show the respective output. So I was calling the respective module whenever it is required, like this

module logic(
        output [3:0] AdderSum,
        output AdderC_out,
        input [3:0] AdderO1, AdderO2, 
        input AdderC_in, AdderClk
    );
    always@(posedge AdderClk)
    begin
        fullAdder4bit FAbit (AdderSum[3:0] , AdderC_out , AdderO1[3:0] , AdderO2[3:0] , AdderC_in);
    end
endmodule


// 4-bit Full ADDER Syntax
//  module fullAdder4bit(output [3:0] sum, output c_out, input [3:0] a, b, input  c_in);

But it gave ERROR :

Instantiation is not allowed in sequential area except checker instantiation

Upvotes: 1

Views: 322

Answers (1)

Qiu
Qiu

Reputation: 5751

Instantiation should be outside always block. On each positive edge of AdderClk, you can just load the results from full adder to a register.

module logic(
    output [3:0] AdderSum,
    output AdderC_out,
    input [3:0] AdderO1, AdderO2, 
    input AdderC_in, AdderClk
);

reg [3:0] sum_r = 4'd0;
reg       c_r   = 1'b0;

wire [3:0] sum_b;
wire       c_b;

fullAdder4bit FAbit (sum_b, c_b, AdderO1, AdderO2, AdderC_in);

always@(posedge AdderClk)
    begin
        sum_r <= sum_b;
        c_r   <= c_b;
    end

assign AdderSum = sum_r;
assign AdderC_out = c_r;

endmodule

The code can be simplified. I wanted to demonstrate the idea behind it. A division operation can be achieved using logic described @Math.

PS I would change the module name, since logic is a keyword in SystemVerilog.

Upvotes: 2

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