No Signal Shown in Isim simulation

Question

i am working on a vhdl code which is supposed to do many functionalities.my code and also my test bench are working fine. but in simulation nothing is initialized. and i dont really understand why and where exactly is my mistake.i would appreciate if someone help me with my problem. "the code should work when enable is '1' and in rising_edge clk. and with different values of S it should do different things.

errors on my simulation are:

ERROR: at 0 ps: Delay 20000 fs is not greater than previous waveform element delay 20000 fs in assignment for target signal a ERROR: In process MyProject_tb.vhd:34

my code is:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ALU IS
   port(
      A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      enable : IN STD_LOGIC;
        clk : IN STD_LOGIC;
      s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        carry : OUT STD_LOGIC;
      c : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0)   
   );
END ALU;


ARCHITECTURE Project of ALU is

signal mult : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal temp : std_logic_vector(3 DOWNTO 0);

begin
     p1: PROCESS(enable, clk, s)
     BEGIN
            IF (enable = '1' AND (clk'EVENT AND clk = '1') AND s = "00") THEN
                 -- cyclic shift on B
                  carry <= '0';
                  c(0) <= B(3);
                    l1: FOR i IN 1 TO 3 LOOP
                       c(i) <= B(i-1);
                              END LOOP;
                END IF;
        END PROCESS;
        
        p2 : PROCESS(enable, clk, s)
        BEGIN
             IF (enable = '1') THEN
                    IF (clk'EVENT AND clk = '1') THEN
                     IF (s = "01") THEN
                        --Multiply A and B  
                        c <= "0000";                      
                        carry <= '0';
                        mult <= std_logic_vector(unsigned(A) * unsigned(B));
                              c <= ("0000" & c);
                        c <= mult;
                            END IF;
                        END IF;
                  END IF;
                END PROCESS;
        p3: PROCESS(enable, clk, s)
        BEGIN
            IF (enable = '1') THEN
                IF (clk'EVENT AND clk = '1') THEN
                    IF (s = "10") THEN
                     --Two's Compliment of A
                     carry <= '0';
                     temp <= not A;
                     c <= std_logic_vector(unsigned(temp) + 1);
                        END IF;
                    END IF;
                END IF;
            END PROCESS;
        p4: PROCESS(A , B, enable, clk, s)
        BEGIN
            IF (enable = '1') THEN
                IF (clk'EVENT AND clk = '1') THEN
                       IF (s = "11") THEN
                     --4-bit Comparator
                     c <= "0011";
                     IF (unsigned(A) > unsigned(B)) THEN
                         c <= "1111";
                     elsif (unsigned(A) < unsigned(B)) THEN
                         c <= "0000";
                     END IF;
                        END IF;
                    END IF;
             END IF;
          END PROCESS;
end Project;

and also my test bench:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY alu_test IS
END alu_test;

    ARCHITECTURE test of alu_test IS
       COMPONENT ALU IS
          port(
          A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
          enable : IN STD_LOGIC;
          clk : IN STD_LOGIC;
          s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
          carry : OUT STD_LOGIC;
          c : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0)   
       );
       END COMPONENT;
    
    SIGNAL a : STD_LOGIC_VECTOR(3 downto 0);
    SIGNAL b : STD_LOGIC_VECTOR(3 downto 0);
    SIGNAL c : STD_LOGIC_VECTOR(3 downto 0);
    SIGNAL s : STD_LOGIC_VECTOR(1 downto 0) := "00";
    SIGNAL en : STD_LOGIC := '1';
    SIGNAL cl : STD_LOGIC := '1';
    SIGNAL car : STD_LOGIC;
    
    BEGIN
       uut : ALU PORT MAP(a, b ,en, cl, s , car, c);
    en <= '1';
    cl <= not cl AFTER 20 NS;
    a <= "0001" , "1101" AFTER 20 NS, "1110" AFTER 20 NS;
    b <= "1101" , "0101" AFTER 20 NS, "1111" AFTER 20 NS;
    s <= "01" , "00" AFTER 20 NS, "10" AFTER 20 NS;
    
    END test;

and its how my simulation looks like: enter image description here

Answer 1

The lines

 a <= "0001" , "1101" AFTER 20 NS, "1110" AFTER 20 NS;
 b <= "1101" , "0101" AFTER 20 NS, "1111" AFTER 20 NS;
 s <= "01" , "00" AFTER 20 NS, "10" AFTER 20 NS;

don't do what you most likely expect them to do.

You most likely want a sequence of "0001", "1101" & "1110" for signal a with 20 ns in between. Otherwise (as the error message suggests), you would assign both "1101" and "1110" to a at the same time (after 20 ns), which is not possible. So reformat your lines to something like:

a <= "0001" , "1101" AFTER 20 NS, "1110" AFTER 40 NS;

I would prefer using a wait statement (inside a process) for wiggling the stimulus signals, though, e.g.:

process
begin
    a <= "0001";
    wait for 20 ns;
    a <= "1101";
    -- and so on...

After this there are some errors revealed in your design (ALU) but fixing them would be another question...