CODEWITHSUNDEEP
vhdlsimulationtest-bench
ferdepe
ferdepe

Reputation: 540

How can I get internal signals to testbench in VHDL 97 and ISim?

I'm working in a testbench with VHDL 97 and Xilinx ISim, and I'm looking for a way to know the value of a UUT internal signal (like spy function in Modelsim) from code instead of waveform.

I know that I can do easily with VHDL-2008 and alias but does someone know any alternative?

Thanks,

Upvotes: 2

Views: 5898

Answers (1)

Jim Lewis
Jim Lewis

Reputation: 3983

Step 1: Declare a global signal in a package

package SpyOnMySigPkg is
  -- synthesis translate_off 
  signal GlobalMySig : std_logic ; 
  -- synthesis translate_on 
end package SpyOnMySigPkg ;

Step 2: Reference the package and assign to the global signal in your design:

use work.SpyOnMySigPkg.all ;
entity MyDesign is 
....
    -- synthesis translate_off 
    GlobalMySig <= MySig ; 
    -- synthesis translate_on

Step 3: Reference the package and read the signal in your testbench:

use work.SpyOnMySigPkg.all ;
entity tb is 
....
  process (GlobalMySig) 
  begin
    if GlobalMySig = '1' then ...

Upvotes: 3

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