How do I fix "Latches may be generated from incomplete case or if statements" messages?

Question

I was trying to do ALU for 4 bit.
I'm getting the correct output. But, while doing RTL Schematics and Technology Schematics, I'm getting errors like this:

Signal missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result.

Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

I wrote this code:

module alu4bit(
    input [3:0] a, b, s,            //  a = Operand_1 , b = Operand_2, s = Select
    output reg [7:0] y , remainder, //   y = outPut
    output reg negative
 );

 always @ (s)
    begin
        case(s)
            4'b0000: begin
                        negative = 0;
                        remainder <= 0;
                        y<= a+b;                        // Addition
                    end
                              
            4'b0001: begin
                        if(a<b) begin
                            y<= b-a;
                            negative =1;
                        end                             // Substraction
                        else begin
                                negative = 0;
                                y<= a-b;
                            end
                        end
                                
            4'b0010: begin
                        negative = 0;
                        remainder <= 0;
                        y<= a*b;                        // Multiplication
                    end
                              
            4'b0011: begin
                        if(a<b) begin
                            y<= 0;
                            remainder <= a;
                        end                             // Division  a/b
                        else begin
                                y <= a/b;
                                remainder <= a - (b*y);
                            end
                        end
            default: begin
                        negative = 0;
                        remainder <= 0;                 // Default  
                        y <= 0;
                    end
                              
        endcase
    end
endmodule

1] What is wrong in this?
2] What is Latches may be generated from incomplete case or if statements?

Answer 1

The reason you see the "Signal missing in the sensitivity list" message is because you only have one of the required signals in the sensitivity list of the combinational always block. Change:

 always @ (s)

to:

 always @*

That syntax automatically includes everything that is needed: s, a, b.

The reason you see the "Latches may be generated" message is because you don't make an assignment to all signals in all branches of your case statement. You did not make an assignment to negative in the 4'b0011 case and remainder in the 4'b0001 case.

---

I also see a problem here:

                            y <= a/b;
                            remainder <= a - (b*y);

You have y on both the RHS and the LHS of assignments in combinational logic. This creates a combinational feedback loop.

Finally, good coding practices recommend using blocking assignments = instead of nonblocking (<=) in combo logic.