Reputation: 33
I have following lines of Verilog code:
mySwitch simblock_out_a_inst0 (.aa(simblock_if_h[0].simblock_out_a),.bb(BLOCK_out_a_inst0),.CloseIfHi(simblock_if_h[0].enable));
mySwitch simblock_out_b_inst0 (.aa(simblock_if_h[0].simblock_out_b),.bb(BLOCK_out_b_inst0),.CloseIfHi(simblock_if_h[0].enable));
mySwitch simblock_out_c_inst0 (.aa(simblock_if_h[0].simblock_out_c),.bb(BLOCK_out_c_inst0),.CloseIfHi(simblock_if_h[0].enable));
mySwitch simblock_out_d_inst0 (.aa(simblock_if_h[0].simblock_out_d),.bb(BLOCK_out_d_inst0),.CloseIfHi(simblock_if_h[0].enable));
mySwitch simblock_out_a_inst1 (.aa(simblock_if_h[1].simblock_out_a),.bb(BLOCK_out_a_inst1),.CloseIfHi(simblock_if_h[1].enable));
mySwitch simblock_out_b_inst1 (.aa(simblock_if_h[1].simblock_out_b),.bb(BLOCK_out_b_inst1),.CloseIfHi(simblock_if_h[1].enable));
mySwitch simblock_out_c_inst1 (.aa(simblock_if_h[1].simblock_out_c),.bb(BLOCK_out_c_inst1),.CloseIfHi(simblock_if_h[1].enable));
mySwitch simblock_out_d_inst1 (.aa(simblock_if_h[1].simblock_out_d),.bb(BLOCK_out_d_inst1),.CloseIfHi(simblock_if_h[1].enable));
The above does work. But the above is for just 2 instances and the code can increase with multiple instances, which I am looking to avoid. Also, I would like to have the number of instances parameterized.
I was thinking of using generate
statement, but due to net names like BLOCK_out_d_inst1
(i.e. in non-array format), I'm unaware of how to implement that.
Any suggestions? Can I create a variable say, var_net
, and use its value as a net? E.g.:
var_net = BLOCK_out_d_inst1;
mySwitch simblock_out_d_inst1 (.aa(simblock_if_h[1].simblock_out_d),.bb(var_net),.CloseIfHi(simblock_if_h[1].enable));
Upvotes: 1
Views: 199
Reputation: 62037
Assuming your BLOCK_out_a_inst0
, etc., signals are 1-bit wide, you can create new bus wires, concatenating the signals together, then use a generate
:
wire [1:0] BLOCK_out_a_inst = {BLOCK_out_a_inst1, BLOCK_out_a_inst0};
wire [1:0] BLOCK_out_b_inst = {BLOCK_out_b_inst1, BLOCK_out_b_inst0};
wire [1:0] BLOCK_out_c_inst = {BLOCK_out_c_inst1, BLOCK_out_c_inst0};
wire [1:0] BLOCK_out_d_inst = {BLOCK_out_d_inst1, BLOCK_out_d_inst0};
genvar i
for (i=0; i<2; i=i+1) begin : switch_num
mySwitch simblock_out_a_inst (.aa(simblock_if_h[i].simblock_out_a), .bb(BLOCK_out_a_inst[i]), .CloseIfHi(simblock_if_h[i].enable));
mySwitch simblock_out_b_inst (.aa(simblock_if_h[i].simblock_out_b), .bb(BLOCK_out_b_inst[i]), .CloseIfHi(simblock_if_h[i].enable));
mySwitch simblock_out_c_inst (.aa(simblock_if_h[i].simblock_out_c), .bb(BLOCK_out_c_inst[i]), .CloseIfHi(simblock_if_h[i].enable));
mySwitch simblock_out_d_inst (.aa(simblock_if_h[i].simblock_out_d), .bb(BLOCK_out_d_inst[i]), .CloseIfHi(simblock_if_h[i].enable));
end
Upvotes: 2