CODEWITHSUNDEEP
bufferverilog
P.goutham
P.goutham

Reputation: 51

IO buffer design using tristate

Program for IO Buffer. All ports are single bit as shown in the below block diagram. When op_en is high, data_out will be driving io_port. When op_en islow, io_port is tri-stated. Data_in will always be connected to io_port.

enter image description here

I tried below code.

module IOBuff(op_en,data_out,io_port,data_in);
input op_en;
inout io_port;
reg data_out;
reg data_in;
begin
assign io_port = op_en ? data_out : `bz
end
endmodule

I am new to verilog and tried above code but it's not complete and also how can we check whether our code is correct or not?

Upvotes: 1

Views: 1243

Answers (1)

ToTamire
ToTamire

Reputation: 1693

  1. In 'bz expression you used grawis (`) instead of apostrophe (').
  2. You don't finish assign expression with comma (;).
  3. Your data_out is type of reg instead of input (depending on image).
  4. Your data_in is type of reg instead of output (depending on image).
  5. You should not place assign inside begin end.
  6. You have unused data_in signal.
module IOBuff(op_en, data_out, io_port, data_in);

    input op_en;
    inout io_port;
    input data_out;
    output data_in;

    assign io_port = op_en ? data_out : 'bz;

endmodule

Upvotes: 1

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