CODEWITHSUNDEEP
fpgaram
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Reputation: 1

how to use Xilinx FPGA RAM?

For example

entity xilinx_TDP_RAM is
  generic(
    ADDR_WIDTH : integer := 32;
    DATA_WIDTH : integer := 129;
    ENTRIES    : integer := 32  -- number of entries  (should be a power of 2)
    );
  port(
    clk : in std_logic;  -- clock

    addra : in std_logic_vector(ADDR_WIDTH-1 downto 0);  -- Port A Address bus, width determined from RAM_DEPTH
    addrb : in std_logic_vector(ADDR_WIDTH-1 downto 0);  -- Port B Address bus, width determined from RAM_DEPTH
    dina  : in std_logic_vector(DATA_WIDTH-1 downto 0);  -- Port A RAM input data
    dinb  : in std_logic_vector(DATA_WIDTH-1 downto 0);  -- Port B RAM input data

    wea : in std_logic;  -- Port A Write enable
    web : in std_logic;  -- Port B Write enable
    ena : in std_logic;  -- Port A RAM Enable, for additional power savings, disable port when not in use
    enb : in std_logic;  -- Port B RAM Enable, for additional power savings, disable port when not in use

    douta : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- Port A RAM output data
    doutb : out std_logic_vector(DATA_WIDTH-1 downto 0)   -- Port B RAM output data
    );
end xilinx_TDP_RAM;

What are the relations about ADDR_WIDTH & DATA_WIDTH & ENTRIES ? DATA_WIDTH must be 2**N ? THX!

Upvotes: 0

Views: 156

Answers (1)

fgagnaire
fgagnaire

Reputation: 898

This is not an xilinx interface. but I think we can still give an answer to your question:

ADDR_WIDTH is typically be equal to:

ceil(log2(real(ENTRIES)))

without looking at the implementation, DATA_WIDTH can be equal to anything positive (in the limit of your FPGA resources).

as a side note, the memery I used from Xilinx is xpm_memory_tdpram

Upvotes: 0

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