CODEWITHSUNDEEP
verilogfpgaramsynthesisquartus
sujeto1
sujeto1

Reputation: 411

I want to use the ram in my FPGA Altera DE1-SOC, am I taking the correct way?

So I created this module which is suppose to represent a RAM, on which I save some data accordingly to the results on my top module.

module RAM_OUT (pix_val, w_mem_out, set_ram);


input [2:0] w_mem_out;
input [31:0] pix_val;
input set_ram;



reg [15:0] addr_out;


reg [31:0] mem_out1 [0:57599];
reg [31:0] mem_out2 [0:57599];
reg [31:0] mem_out3 [0:57599];

/////////// ram out ///////////////

always @ (w_mem_out or set_ram)
begin

if (set_ram)
addr_out = 0;

else 
    begin

        if (w_mem_out == 1)

                begin
                mem_out1 [addr_out] = pix_val;  
                mem_out2 [addr_out] = 32'b11111111_000000000000000000000000;
                mem_out3 [addr_out] = 32'b00000000_000000000000000000000000;

                addr_out = addr_out + 16'b0000000000000001;
                end

        else if (w_mem_out == 2)        

                begin
                mem_out1 [addr_out] = 32'b11111111_000000000000000000000000;
                mem_out2 [addr_out] = pix_val;  
                mem_out3 [addr_out] = 32'b00000000_000000000000000000000000;

                addr_out = addr_out + 16'b0000000000000001;
                end

        else if (w_mem_out == 3)        

                begin
                mem_out1 [addr_out] = 32'b11111111_000000000000000000000000; 
                mem_out2 [addr_out] = 32'b11111111_000000000000000000000000;
                mem_out3 [addr_out] = pix_val;

                addr_out = addr_out + 16'b0000000000000001;
                end

        else    

                addr_out = addr_out;

    end
end

endmodule

The program already works perfectly fine on simulation, but since I'm planning to load it into my FPGA, I want to use the SDRAM memories available in the board (my intention is to make a full SOC, and I need to load the data to the SDRAM, then use my design to process such data).

So, I wonder if programming the SDRAM is too far from what I did in the code above. You can see there is are some logic I wrote in order it save the data I want into the "memories" but I'm not sure if this is same when doing the SDRAM or I will have to later change my design for this (I would not like this since my system is already working good in simulation).

I wrote the code above reading from altera documentation, they say this is the way to make a RAM, but is this synthesizable? What is really happening in the FPGA, it inferers memory using the gates in the FPGA chip or make use of the actual memory of the board? Please note, input data is composed of 57600 32bits numbers.

Upvotes: 1

Views: 2950

Answers (2)

Prashant
Prashant

Reputation: 362

The code that you have written would be synthesized to internal RAM blocks or LUT-based RAMs. They will not utilize the SDRAM on the board

The internal RAM of an FPGA generally has a single clock cycle access and the path through these RAMs is included in the Static Timing Analysis that is usually performed after Place and Route (PAR).

If you wish to use the on-board SDRAM, you will have to include a dedicated SDRAM controller, which will consume finite logic inside the FPGA. The access times for these on-board SDRAMs would typically be a few clock cycles and would be bursty in nature.

External SDRAMs are typically used to store large volumes of data such as packet payloads or equivalent while on-chip RAMs are used to store local data such as headers, temporary processing results, etc.

Upvotes: 1

Matthew
Matthew

Reputation: 13987

If you are using an FPGA synthesising a RAM is not a bad idea. A good way of doing it is to design a module that behaves like a RAM and then to instantiate that module in the rest of your code. So,

i) your RAM module should have suitable inputs and outputs: address bus(ses), input data bus, output data bus, control signals (write enable etc), clock...

ii) your RAM module should contain an array

iii) your RAM module should contain one or more always blocks and/or assign statements to implement the behaviour of a RAM.

Here is an example, which should synthesise to a RAM using an FPGA synthesiser:

module RAM(
  input        clock,            // best to make it synchronous
  input        write_enable,     // a simple active high write enable
  input [3:0]  address,          // a single address bus in this example
  input [7:0]  data_in,          // input data
  output [7:0] data_out);        // output data

  reg [7:0] mem [0:15];          // here is the array; make this the size you need

  always @(posedge clock)
    if (write_enable)
      mem[address] <= data_in;

  assign data_out = mem[address];

endmodule

Upvotes: 1

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