CODEWITHSUNDEEP
verilogsystem-verilog
Meleth
Meleth

Reputation: 36

Mask a field on a packed struct in SystemVerilog

I am looking for the best way to mask a field inside a packed struct.

Imagine you have:

typedef struct packed {
  logic [5:0] add;
  logic [3:0] data;
  logic [1:0] control;
} mytype;

I want to assign to a new signal a signal with the data masked to zero. In my case, the struct has many fields so I prefer not to assign them one by one if possible, like this:

my_type new_signal;

assign new_signal.add     = old_signal.add;
assign new_signal.data    = '0;
assign new_signal.control = old_signal.control;

I need it to compare the old signal against a different signal, except for 3 fields.

Upvotes: 0

Views: 801

Answers (2)

Serge
Serge

Reputation: 12354

Another way is to use 'packed' vector for the struct. If you know your offsets in the struct you can build a mask. In your case the following will work:

new_signal = old_signal & 12'b111111_0000_11;
------------------------------^^^^^^_----_^^
                              add....data.control

Upvotes: 1

dave_59
dave_59

Reputation: 42673

You can do this in procedural code by assigning the whole signal first, then assigning the individual fields you want to mask out.

always_comb begin
    new_signal = old_signal;
    new_signal.data    = '0;
end

Upvotes: 3

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