CODEWITHSUNDEEP
vhdl
gyuunyuu
gyuunyuu

Reputation: 684

Is there a way in VHDL to external name reference a generic?

A module lower in the hierarchy has integer generics. I want to override the generic inside this automatically generated code from my testbench by using VHDL force command. The problem is that whatever I do the simulator gives error message:

# ELAB2: Fatal Error: ELAB2_0127 W_PROBE_FPGA.vhd (136): Incorrect object class for external name: '<<probe_fpga_inst.SPRINT_PROBE_TOP_LEVEL_0.SYNTHESIZE_ACCELERATION_DAQ>>'.

I tried this code:

alias SYNTHESIZE_ACCELERATION_DAQ is <<signal probe_fpga_inst.SPRINT_PROBE_TOP_LEVEL_0.SYNTHESIZE_ACCELERATION_DAQ : integer>>;

With keywords signal, variable, constant and also empty. But none of them work. What do I do now?

Upvotes: 0

Views: 761

Answers (1)

Jim Lewis
Jim Lewis

Reputation: 3973

You can see from @Tricky's response that external names are not going to get the job done. However, you can use a configuration declaration to do it.

Configuration declarations can be hierarchical and can set generics as shown below. Below for entity/component Block1 (whose instance label is Block1_1) the value for generic G1 is changed to NewValue. Note for generic G2, the mapping done preserves the value.

library LIB_CHIP ; 
configuration CfgLower of TbCHIP is
  for StructTb
    for CHIP_1 : CHIP 
      use entity LIB_CHIP.CHIP (StructChip) ;
      for Structural
        for Block1_1 : Block1
          use entity work.Block1(RTL) 
          generic map (G1 => NewValue, G2 => G2) ; 
        end for ; 
      end for ; 
    end for ; 
  end for ;
end CfgLower ;

For synthesis, you would need to "propagate up generics" by putting a lower level generic on a higher level design until you get to the level at which you are using the higher level component.

entity NextHigher is
  generic (G1 : integer ) ; 
  port (...) ; 
end entity NextHigher ;
architecture RTL of NextHigher is

begin
  Lower_1 : Lower
    generic map (G1 => G1) -- mapping Generic from NextHigher to Lower
    port map (. . . ) ; 

  . . . 
end architecture RTL ; -- NextHigher

Upvotes: 2

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