CODEWITHSUNDEEP
verilogshift
Xhulio Xhelilai
Xhulio Xhelilai

Reputation: 45

Why is shift command not working in concatenation in Verilog?

enter image description hereI am posting all the code here.

I get warnings in concatenation in the always block which I don't get:

concatenation with unsized literal; will interpret as 32 bits

module DECSTAGE(
    input [31:0] Instr, ALU_out,MEM_out,
     input RF_WrEn,RF_WrData_sel,RF_B_sel,
     input Clk,
     output reg [31:0]Immed,
     output [31:0] RF_A,RF_B
    ); 
     
    wire [5:0]Opcode,func;
    wire [4:0]rs,rd,rt;
    wire [15:0]Immediate ;
    /*
        Decoding instruction in:
        - Opcode
        - rs,rd,rt
        - func
        - Immediate
    */
    assign Opcode[5:0] = Instr[31:26];
    assign rs[4:0] = Instr[25:21];
    assign rd[4:0] = Instr[20:16];
    assign rt[4:0] = Instr[15:11];
    assign func[5:0] = Instr[5:0];
    assign Immediate[15:0] = Instr[15:0];
    
    // Needed variables for always block
    reg [4:0]adr2;
    reg [31:0]din;
    // Creating the Register File with 32 registers
    Register_File_RF rgf_RF (.Adr1(rs),.Adr2(adr2),.Awr(rd),.Dout1(RF_A),.Dout2(RF_B),.Din(din),.WrEn(RF_WrEn),.Clk(Clk));
    
    
    always @(posedge Clk)begin
        
        // MUX for rd/rt
        if (RF_B_sel)begin
            adr2 = rd;
        end else begin
            adr2 = rt;
        end
        
        // MUX for ALU_out/MEM_out
        if (RF_WrData_sel)begin
            din = ALU_out;
        end else begin
            din = MEM_out;
        end
        
        // Selecting the Operation for the Immediate
        // SignExtend(Immediate)
        if (Opcode == 6'b111000 || Opcode == 6'b110000 || Opcode ==6'b000111 || 6'b001111 || 6'b011111)begin
            Immed = {{16{Immediate[15]}}, Immediate[15:0]};
        // Immediate << 16 (zeroFill)
        end else if (Opcode == 6'b111001)begin
        
            Immed = {{Immediate[15:0]},{16{0}}};
        
        // ZeroFill(Immediate) 
        end else if (Opcode == 6'b110010 || Opcode == 6'b110011)begin
            Immed = {{16{0}},Immediate[15:0]};
        
        // SignExtend(Immediate)<<2
        end else if (Opcode ==6'b111111 || Opcode == 6'b000000 || Opcode == 6'b000001)begin
            Immed = {{16{Immediate[15]}},Immediate[15:0]}<<2;
        
        // ZeroFill(Immediate) (7 downto 0)
        end else if (Opcode == 6'b000011)begin
            Immed = {{16'b000000000000000000000000},Immediate[7:0]};
        end
    end
    
endmodule

According to my simulations, Immed is a 32bit, takes the sign of Immediate[15] in all 16 bits, takes the Immediate[15:0] in the remaining bits but it never does the shift command.

Here's my simulation:

initial begin
    // Initialize Inputs
    Instr = 0;
    ALU_out = 0;
    MEM_out = 0;
    RF_WrEn = 0;
    RF_WrData_sel = 0;
    RF_B_sel = 0;
    Clk = 0;

    #20;
    Instr = 32'b11111100000000000000000000000011;
    RF_B_sel = 1;
    
    // Add stimulus here

end

Upvotes: 1

Views: 118

Answers (1)

toolic
toolic

Reputation: 62037

You never execute the line with the shift because the if condition is always true. The following line is always true because you mistakenly omitted Opcode == for the last 2 comparisons:

    if (Opcode == 6'b111000 || Opcode == 6'b110000 || Opcode ==6'b000111 || 6'b001111 || 6'b011111)begin

Change the line to:

    if (Opcode == 6'b111000 || Opcode == 6'b110000 || Opcode ==6'b000111 ||  Opcode ==6'b001111 ||  Opcode ==6'b011111)begin

You get warnings because the replicated concatenation syntax is illegal. You need to use a sized literal instead of 0. You need to change:

{16{0}}

to:

{16{1'b0}}

Upvotes: 1

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