CODEWITHSUNDEEP
verilogsystem-verilogsystem-verilog-assertions
Meleth
Meleth

Reputation: 36

SVA Signal doesn't change while other one is true

This is very basic but I've been blocked the whole afternoon. I need a property to check that if A is set, B cannot change.

         _____________________
A ______/                     \______________
                                                   PASS
B ___________________________________________


         _____________________
A ______/                     \______________
                     ________________________      FAIL
B __________________/

I tried A |-> $stable(B) but that doesn't work

Any idea?

Thank you

Upvotes: 0

Views: 942

Answers (1)

dave_59
dave_59

Reputation: 42788

What you wrote says: "every cycle that A is true, B must be stable in the same cycle". That is a single-cycle assertion.

What you want is

$rose(A) |-> ##1 $stable(B) until !(A);

The ##1 is needed if you do not need the first cycle that A is true for B to be stable.

Upvotes: 2

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