CODEWITHSUNDEEP
moduleenumstypedefsystem-veriloginstantiation
Nisha John
Nisha John

Reputation: 25

Typedef Enum - Instantiation at top module and port connection

I am trying to instantiate a state machine at top level module and connect the states at top level ports to probe them as part of debug. I am trying something like this as in example below:

 .state[0](DEBUG_1),
 .state[1](DEBUG_2),

DEBUG_1 and DEBUG_2 are output ports in the top level module, and I want to probe these signals at the top logic.

The above is not working in SystemVerilog and gives errors. How else can this be done?

      package states;

      typedef enum logic [2:0] {RE = 3'b000, 
                    NOR = 3'b001, 
                    WD = 3'b011,
                    TO = 3'b010,
                    EVL = 3'b110,
                    DEC = 3'b111} state_t;

       endpackage

     import states::*; 
     module fsm (
     input                   clk,                    
     input                   reset,
      output  state_t state
     );

    import rtl_pkg::*;
    import states::*; 
    module top (
    output   logic        DEBUG_1,                       
    output   logic        DEBUG_2                      
    );  

 fsm fsm_inst (
.clk(sys_clk),                    
.reset(sys_reset), 
.state[0](DEBUG_1),
.state[1](DEBUG_2),
.state[2](DEBUG_3),
);

 ERROR - (VERI-1137) syntax error near '['
 ERROR -  module top ignored due to previous errors

Upvotes: 1

Views: 514

Answers (1)

toolic
toolic

Reputation: 62037

Here is one way to get rid of the compile errors:

module top (
    output   logic        DEBUG_1,                       
    output   logic        DEBUG_2, DEBUG_3                      
);  

     // ... signal declarations

     fsm fsm_inst (
        .clk   (sys_clk),                    
        .reset (sys_reset), 
        .state ({DEBUG_3, DEBUG_2, DEBUG_1})
    );
endmodule

Concatenate the 3 DEBUG bits using {}, then connect it directly to the state port.

Upvotes: 1

Related Questions