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Daniel
Daniel

Reputation: 7724

Using enum in verilog

I'm writting a piece of code in Quartus verilog (.v) and I'm trying to write a enum type inside my module:

module Controller(clk, IorD);

    enum {READ, DECODE} state;
    myState = READ;
    //...

But it gives me the following error: Error (10170): Verilog HDL syntax error at Controller.v(3) near text "{"; expecting ";".

What am I doing wrong? How can I use a enum in verilog?

Upvotes: 1

Views: 22249

Answers (4)

ToTamire
ToTamire

Reputation: 1703

enum is not a part of IEEE Std 1364-2005 specification (newest Verilog specification).

You have to use SystemVerilog which support enum or make a workaround in Verilog:

parameter READ   = 'd 0;
parameter DECODE = 'd 1;

my_state = STATE_READ;

I suggest placing all parameters in second file with extension .vh (Verilog Header) and include them by `include directive. For example:

`include "parameters.vh"

You can also notice that I used my_state except myState because in Verilog naming conventions suggest to use lowercase with underscores (_) to separate words.

Upvotes: 3

varsityblue
varsityblue

Reputation: 1

You will need to use typedef.

In your case =>

module Controller(clk, IorD);

typedef enum {READ, DECODE} state_e;

state_e myState;

//Now you can use myState ...

Upvotes: -2

Prasad Addagarla
Prasad Addagarla

Reputation: 31

You can instead use parameters in place of enums if you are restricted to using verilog only in the tool. If you can switch to other tools try edaplayground(dot)com

example code as requested below:

localparam START =1;
localparam STOP  =2;

Use localparam instead of parameter because you really don't want these values to be changed during instantiation.

Upvotes: 3

gatecat
gatecat

Reputation: 1186

enum is a SystemVerilog feature. You will need to make sure that the file type in Quartus is SystemVerilog (usually the .sv extension is used too)

Upvotes: 4

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