CODEWITHSUNDEEP
enumsverilogsystem-verilog
Nan
Nan

Reputation: 247

Enumerated type as input or output

In Systemveilog, is there any way that one can pass an enum type variable to other modules? That is, to define an enum type variable as either input or output. Is there any example available?

Upvotes: 2

Views: 3487

Answers (1)

dave_59
dave_59

Reputation: 42788

Yes, you can do this, but you need to use a typedef in a common package to make the enums assignment compatible. Then you can use an enum in a port just like any data type. 

package myCommon;
  typedef enum {ONE,TWO} e_t;
endpackage
module first import myCommon::*; (output e_t p1);
endmodule
module second import myCommon::*; (input e_t p2);
endmodule
module top;
  import myCommon::*;
  e_t e;
  first f(.p1(e));
  second s(.p2(e));
endmodule

Upvotes: 3

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