CODEWITHSUNDEEP
verilogsystem-verilog
Ari
Ari

Reputation: 7556

Casting enum to logic

Consider the following module declaration:

module DFF(d, q, CLK, RESET);
 parameter W = 2;
 input  [W-1:0] d;                      
 input  CLK;                                
 input  RESET;      
 output logic [W-1:0]   q; 

//....
endmodule

What is the proper way of instantiating it where d and q are of enum type? Here is my enum type:

typedef enum logic [1:0] {ENUM_IDLE = 0,
            ENUM_S1 ,
            ENUM_S2
            } T_STATE;

I would like to instantiate the DFF for a T_STATE variable type:

T_STATE d, q;
DFF dff_inst (.d(d), .q(q), .CLK(CLK), .RESET(RESET));

This generates compile/enumeration error. I have also unsuccessfully tried:

DFF dff_inst (.d(logic'(d)), .q(logic'(q)), .CLK(CLK), .RESET(RESET));

and

DFF dff_inst (.d(logic[1:0]'(d)), .q(logic[1:0]'(q)), .CLK(CLK), .RESET(RESET));

I would like to keep the DFF definition as is, but cast the enum type to logic.

Edit:

This one, suggested in IEEE Std 1800-2012, 6.24.1, also generates an elaboration error:

typedef logic [$bits(T_STATE) - 1 : 0] T_STATE_LOGIC; 
DFF dff_inst (.d(T_STATE_LOGIC'(d)), .q(T_STATE_LOGIC'(q)), .CLK(CLK), .RESET(RESET));

Upvotes: 3

Views: 12130

Answers (1)

Greg
Greg

Reputation: 19122

d doesn't need to be casted.

I could only reproduce the error with ModelSim, all the other simulators I have access to didn't generate any errors or warnings and simulated correctly.

For ModelSim, I found that this worked:

DFF dff_inst (.q(q[1:0]), .*);

and this worked:

DFF dff_inst (.q({q}), .*);

Working example on here

Upvotes: 4

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