VHDL ERROR: formal port 'num' has no actual or default value

Question

I have this compilation error in Vivado when trying to port a simple testing device to setup simulations. This is found when standing on the 'uut : testing_logic' line. I have triple checked my commas and semi-colons, but cannot figure out why I keep getting this error.

I have seen the issue VHDL: formal port 'portName' has no actual or default value and my error is not the same.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity testing_logic_TB is
end testing_logic_TB;

architecture Behavioral of testing_logic_TB is
    -- Declare component to test
    component testing_logic
        port(
            -- stuff in the component
            --inputs
            num : in std_logic_vector(4 downto 0);
            btn_add : in std_logic;
            btn_sub : in std_logic;
            clk : in std_logic;
            reset : in std_logic;
            --Outputs
            led : out std_logic_vector(15 downto 0)
        );
    end component;
    
    -- Declare all signals to change inputs and check outputs
    signal num_TB : std_logic_vector(4 downto 0);
    signal btn_add_TB : std_logic := '0';
    signal btn_sub_TB : std_logic := '0';
    signal clk_TB : std_logic := '0';
    signal reset_TB : std_logic := '0';
    signal led_TB : std_logic_vector(15 downto 0);

    -- Constants needed for simulation
    constant CLK_PERIOD : time := 2 ns;

begin
    
    uut : testing_logic
        port map(
            num : num_TB,
            btn_add : btn_add_TB,
            btn_sub : btn_sub_TB,
            clk : clk_TB,
            reset : reset_TB,
            led : led_TB
        );

    --Change the clock
    clk_change : process
    begin
        clk <= '0';
        wait for CLK_PERIOD / 2;
        clk <= '1';
        wait for CLK_PERIOD / 2;
    end process;

    -- change reset
    rst_change : process
        rst <= '1';
        wait for CLK_PERIOD * 10;
        rst <= '0';
        wait for CLK_PERIOD * 10;
        rst <= '1';
        wait for CLK_PERIOD * 10;
        rst <= '0';
        wait for CLK_PERIOD * 10;
    end process;

    -- change number
    num_change : process
        num_TB <= 10;
        wait for CLK_PERIOD * 2;
        num_TB <= 5;
        wait for CLK_PERIOD * 2;
    end process;

    -- press add button
    press_btn_add : process
        btn_add_TB <= '1';
        wait for CLK_PERIOD / 10;
        btn_add_TB <= '0';
        wait for CLK_PERIOD * 3;
    end process;
    
    -- press subtract button
    press_btn_sub : process
        wait for CLK_PERIOD * 3;
        btn_sub_TB <= '1';
        wait for CLK_PERIOD / 10;
        btn_sub_TB <= '0';
    end process;

end Behavioral;

Answer 1

To your problem is just that you don't use the proper syntax for port mapping your this is the correct syntax

    uut : testing_logic
    port map(
        num =>num_TB,
        btn_add => btn_add_TB,
        btn_sub => btn_sub_TB,
        clk => clk_TB,
        reset => reset_TB,
        led => led_TB
    );