CODEWITHSUNDEEP
verilog
Johnmph
Johnmph

Reputation: 3391

Assign multiple values to one latch

I need a latch which can take multiple bus with one enable signal for each and when this signal is high, the latch takes the value of the associated bus, something like this :

enter image description here

I tried this :

module Test (
    input [1:0] load,
    input [15:0] bus,
    output reg [7:0] value
);

    wire [7:0] temp;
    
    assign temp = (load[0]) ? bus[7:0] : (load[1]) ? bus[15:8] : 8'bZZ;
    
    always @(load or temp) begin
        // Latch value
        if (load) begin
            value <= temp;
        end
    end
    
endmodule

and this :

module Test (
    input [1:0] load,
    input [15:0] bus,
    output reg [7:0] value
);
    
    always @(load or bus) begin
        // Latch value
        if (load[0]) begin
            value <= bus[7:0];
        end
        else
        if (load[1]) begin
            value <= bus[15:8];
        end
    end
    
endmodule

And this same warning appears on both (repeated for each bit) :

Warning (13012): Latch Test:test|value[0] has unsafe behavior

Warning (13013): Ports D and ENA on the latch are fed by the same signal load[0]

The only way that I found to avoid these warnings is like this :

module Test (
    input [1:0] load,
    input [15:0] bus,
    output [7:0] value
);
    
    reg [15:0] temp;
    reg index;
    
    always @(load or bus) begin
        if (load[0]) begin
            index <= 0;
        end
        else
        if (load[1]) begin
            index <= 1;
        end
        
        // Latch value
        if (load) begin
            temp <= bus;
        end
    end
    
    assign value = temp[8*index+7 -:8];
    
endmodule

But it's a waste of memory because it saves the two buses instead of one, is it possible to do it with one reg and avoiding these warnings ?

Upvotes: 0

Views: 269

Answers (1)

dave_59
dave_59

Reputation: 42788

I don't think you can get rid of the warnings in the first two examples—you have a bonafide race condition between the latch enable and the data feeding the latch. It is more obvious in your first example.

When load goes to 0, temp will be changing to Z ( a don't care most likely 0) at the same time the latch enable goes to 0. Which one happens first is clearly a race.

Upvotes: 1

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