CODEWITHSUNDEEP
assemblycpu-architectureinterruptspecificationsriscv
sven
sven

Reputation: 126

Why User-mode interrupt was introduced in RISC-V?

In RISC-V privileged architecture V1.11 or draft of version 1.12, "N" extension is introduced for User-level interrupts, hardware which implemented this extension can transfer control directly to a user-level trap handler without invoking the outer execution environment.

But there are mirrored CSR and instruction for the N extension, for a system which support M and U mode only, the both save and restore similar context for interrupts, so why the N extension introduced and what benefit can we get?

Upvotes: 3

Views: 1276

Answers (1)

Timmmm
Timmmm

Reputation: 97008

I found this paper User Mode Interrupts - A Must for Embedded Systems that might be interesting. I skimmed it and it is very vague and not very well written, but the motivation seems to be security - to keep exception/interrupt handling out of the kernel. Similar to how FUSE keeps filesystem code out of the kernel. I'm not sure I'm overly convinced by that.

The spec said:

When used in an Unix environment, the user-level interrupts would likely not replace conventional signal handling, but could be used as a building block for further extensions that generate user-level events such as garbage collection barriers, integer overflow, floating-point traps.

Again I'm not sure about that. Interrupts are a really horrible (but sometimes necessary) pre-emption mechanism. I don't know why you'd want more of them.

When it was removed from the ISA manual in 2021, Andrew Waterman said:

Zeitgeist on mailing list is that, if something N-like is to be adopted (for purposes that bare S mode can't cater to), it'll likely need to be redesigned.

It isn't currently listed on the extension status page at all, so it seems like nobody really wants it that much.

Upvotes: 3

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