CODEWITHSUNDEEP
multiprocessingcpu-cachethread-synchronizationmemory-model
akreuzkamp
akreuzkamp

Reputation: 31

Cache coherence for a data race free programs

All examples I've ever seen on when cache coherence is relevant are code examples that are data races (two cores simultaneously write to the same memory location).

When it comes to memory consistency, hardware vendors have decided not to provide serial consistency guarantees and e.g. C++11 has adopted the SC for DRF memory model, which basically says, if you want serial consistency, make sure your program doesn't have data races.

Why isn't the same approach applied to cache coherency? That is, a data race free program doesn't need transparent cache coherency and cache lines are synchronized exactly where the programmer/compiler inserted a synchronization barrier.

Or put in another way: Why worry about cache coherence if it is only relevant for race conditions?

Upvotes: 0

Views: 178

Answers (1)

pveentjer
pveentjer

Reputation: 11392

All examples I've ever seen on when cache coherence is relevant are code examples that are data races (two cores simultaneously write to the same memory location).

A concurrent write/write or a concurrent read/write to the same memory location is a data-race; not just a concurrent write/write.

When it comes to memory consistency, hardware vendors have decided not to provide serial consistency guarantees

You mean sequential consistency.

Or put in another way: Why worry about cache coherence if it is only relevant for race conditions?

I guess you mean data-races. Race conditions are a higher-level problem.

I'm not sure what your question is. You need to understand that coherence equivalent to sequential consistency for a single location. So any system that is sequentially consistent, is automatically coherent.

Upvotes: 0

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