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Reputation: 390

SystemVerilog QuestaSim - Pass string to $fdumpvars to save multiple VCD files

I am trying to generate multiple VCD file inside the same initial begin in QuestaSim 2021.3 (latest).

I found this section in the QuestaSim user manual: enter image description here

But, I am only able to pass a "/hardcoded/path/to/vcdfile.vcd" as filename, and this is true for a single VCD file.

Here's my code:

module adder(
 input logic clk,
 input logic rstn,
 input logic [31:0] a, b,
 output logic [31:0] sum
) ;

  always_ff @ (posedge clk or negedge rstn)
    if (!rstn) sum <=0;
    else sum <= a + b;
endmodule: adder

module tb;
 
  logic clk;
  logic rstn;
  logic [31:0] a, b;
  logic [31:0] sum;

  adder i_adder (
    .clk  (clk),
    .rstn (rstn),
    .a    (a),
    .b    (b),
    .sum  (sum)
  );
 
  always begin
    #1us clk = ~clk;
  end
  
  initial begin
    
    string dump1 = "dump1.vcd";
    string dump2 = "dump2.vcd";
    
    $fdumpfile(dump1);
    $fdumpvars(1, i_adder.a, dump1);
   
    clk = 0;
    rstn = 0;
    a = 4;
    b = 2;
    
    #10us
    rstn = 1;
    
    #10us
    $display("Sum: %d",i_adder.sum);
    
    $fdumpoff(dump1);
    $fdumpall(dump1);
    $exit;
  end

No VCD file is exported, and QuestaSim throws an error:

# ** Error (suppressible): (vsim-PLI-3111) $fdumpvars : Last argument must be a filename.

I have a playground with this code on EdaPlayground.

To be clear, I tried:

$typename(dump1); // returns string
$typename("path/to/vcdfile.vcd"); // returns string

So for Questa they are both strings, but the first can not be passed to $fdumpvars()

Upvotes: 1

Views: 705

Answers (2)

Morn
Morn

Reputation: 36

I encountered the same problem. This seems to be a case where QuestaSim does some unnecessary static code checking.

Luckily, the error is "suppressible" and can be disabled using the vsim command line option -suppress 3111. With this option, I was able to write multiple dynamically-named VCD files from QuestaSim.

Upvotes: 1

toolic
toolic

Reputation: 62236

$fdumpvars is not a standard Verilog system task. It is not defined in IEEE Std 1800-2017, which means that it's behavior is specific to the vendor that implemented it, namely QuestaSim.

If you want the task to accept a string variable type as an argument, you should request that functionality directly from the vendor.

Perhaps someone else has already reported this, and there is a newer version of QuestaSim that already has this feature. Again, contact the vendor.

For comparison, the standard Verilog task for dumping a VCD file, $dumpfile, does accept a string variable type:

$dumpfile(dump1);

Upvotes: 0

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