CODEWITHSUNDEEP
verilog
Steve Deltora
Steve Deltora

Reputation: 39

wire value does not change by always instruction

this is my design, calH.v

module calH(
    input clk,
    input rst,
    input [1:0] xin,
    input [15:0] coeff, //4bit per coefficient
    output reg [1:0] xout, //1 bit per x
    output wire [7:0] H_value
);

reg [7:0] H_p; //processed H

always@(posedge clk or negedge rst) begin
    if(~rst) begin //set initial condition
        H_p <= 0;
    end
    else begin //cal H
        H_p <= xin[0]*xin[0]*coeff[15 -: 4];
        H_p <= xin[0]*xin[1]*coeff[11 -: 4];
        H_p <= xin[1]*xin[0]*coeff[7 -: 4];
        H_p <= xin[1]*xin[1]*coeff[3 -: 4];
    end
end

assign H_value = H_p;

endmodule

In always, H_p changes four times and I assign H_value = H_p, so H_value also change four times.

in testbench I give coeff = 16'h1234;

in my design, the H_value results should be 1 --> 2 --> 3 --> 4

but in modelsim simulation it only shows 4. thanks.

enter image description here

Upvotes: 0

Views: 137

Answers (1)

Mikef
Mikef

Reputation: 2508

The variable H_p gets overwritten 3 times; the last assignment wins.

All the changes made to that variable are occurring in 0 time at the positive edge of the clock.

Simulation will not show the overwriting because it happens in 0 time.

Store the results of 4 multiplies by creating 4 registers to hold the 4 outputs. Like this:

module calH(
    input clk,
    input rst,
    input [1:0] xin,
    input [15:0] coeff, //4bit per coefficient
    output reg [1:0] xout, //1 bit per x
    output wire [7:0] H_value
);

  reg [7:0] H_p_0; //processed H
  reg [7:0] H_p_1; //processed H
  reg [7:0] H_p_2; //processed H
  reg [7:0] H_p_3; //processed H

always@(posedge clk or negedge rst) begin
    if(~rst) begin //set initial condition
        H_p_0 <= 0;
        H_p_1 <= 0;
        H_p_2 <= 0;
        H_p_3 <= 0;
    end
    else begin //cal H
        H_p_0 <= xin[0]*xin[0]*coeff[15 -: 4];
        H_p_1 <= xin[0]*xin[1]*coeff[11 -: 4];
        H_p_2 <= xin[1]*xin[0]*coeff[7 -: 4];
        H_p_3 <= xin[1]*xin[1]*coeff[3 -: 4];
    end
end

assign H_value = H_p_0;
// More assignments as needed
  
endmodule

Then combine the 4 registers as needed.

Upvotes: 2

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