CODEWITHSUNDEEP
verilog
sanforyou
sanforyou

Reputation: 455

assign real value to wire in Verilog

Hi I have a simple verilog statements where I want to transfer value at real net to a wire using assign statement. However I see a wire at "x" all the time regardless of the value of a real variable. Here is a snapshot of a sample code with values annotated at time zero:

QN is a wire and real_QN is of type real.

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Any ideas why QN is at "x" even though real_QN is at "0" ?

Upvotes: 0

Views: 9998

Answers (1)

Rich Maes
Rich Maes

Reputation: 1222

So for reference, the "real" type in not synthesizeable. Only mentioning it because it might be relevant. As such, this solution isn't synthesizeable either. But it should work in simulation. You can not just assign one to the other in this case. But there is a function that will do it for you.

real someReal;
reg  [63:1]someReg;

initial begin

someReal = 21.0 ;
$display("someReal---->%f",someReal);
$display("someReg---->%b",someReg);
#1

someReg = $realtobits(someReal);
$display("someReg---->%b",someReg);

Let me know if that does not work for you.

Upvotes: 1

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