CODEWITHSUNDEEP
verilog
Farzan
Farzan

Reputation: 27

Assign value to an array of wires

How can I assign whole values of an array of regs to an array of wires in Verilog? Like this:

[5:0]tag_in=tag_in_reg;

(tag_in_reg is an array of regs and tag_in is an array of wires)

Upvotes: 1

Views: 2688

Answers (2)

Jithin
Jithin

Reputation: 88

You can use Verilog assign statement, that will help you to assign values to an array of wires. 

 module test(output [5:0] tag_in_reg);
  reg [5:0] tag_in;
  assign tag_in_reg=tag_in;
endmodule

Upvotes: 1

Qiu
Qiu

Reputation: 5761

If I understand you correctly, you're looking for a simple assign construct:

assign tag_in = tag_in_reg;

Upvotes: 0

Related Questions