CODEWITHSUNDEEP
verilog
user1637645
user1637645

Reputation: 341

How to write to "wire" and passing parameters to arrays of instances in Verilog

I have the following code:

module X;
    wire [11:0] mga [0:15]; 
    // other code omitted here for clarity

    reg [11:0] globalStartAddresses [0:15];
    reg [11:0] globalEndAddresses [0:15];

    localMMU mmu[0:15](clock, globalStartAddresses, globalEndAddresses, mrw, mdi, mdo, mga);

    task dispatcher;
        // parameters
        output reg dataReady;
        input readWrite;
        input [7:0] dataIn;
        output reg [7:0] dataOut;
        input [11:0] globalAddress;

        // local variables
        integer x, selected;

        begin
            for(x=0; x<16; x=x+1) begin
                if(globalAddress >= globalStartAddresses[x] && globalAddress <= globalEndAddresses[x]) selected=x;
            end

            mrw[selected]=readWrite;
            mdi[selected]=dataIn;       
            assign mga[selected]=globalAddress;

            if(readWrite==1)
                wait(mdo[selected]!=0);
            else
                wait(mdo[selected]!=dataIn);

            dataOut=mdo[selected];
        end
    endtask
endmodule

I get 2 errors in the code:

  1. In the array instance declaration of "localMMU", it states that "globalStartAddress[ ] should be present", but I have declared it just above as is evident.
  2. In the assign statement inside the task, it states that only variables are allowed on LHS.

(I am using VeritakWin 3.84F) Please tell me how can I rectify these 2 problems. Thanks.

Upvotes: 0

Views: 1689

Answers (1)

Mehran Torki
Mehran Torki

Reputation: 987

  1. globalStartAddresses and globalEndAddresses are both of type array but array can not be passed directly between two modules. You must flatten the array into a vector and then pass it to a module. The problem is answered here :

    How to pass array structure between two verilog modules

  2. Left hand side of procedural continuous assignment can not be of type wire while in continuous assignment, left hand side must be just of type wire. As a solution, change mga type to reg. The same problem answered here:

    Continuous assignment verilog

Upvotes: 1

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