CODEWITHSUNDEEP
verilogsystem-verilog
shawn_reeds
shawn_reeds

Reputation: 22

Compilation errors due to operands in if statement

This is a system verilog file .The below code when run gives an error "Illegal operand for constant expression" at "if(m_val !==0) and if(div_val)"

Have tried without generating statements but still the same error. Any help on what is wrong with the code?

logic m_ref_clk,mul_ref_clk,div_ref_clk,mixed_ref_clk;

real clk_period = ((1.0/(freq*BASE_GHz_CLK_FREQ))*1s);





 generate 
if(m_val !== 0) begin
    if(div_val == 0)begin
        initial begin 
          clk_period = clk_period*m_val;
         forever begin 
         #(clk_period) mul_ref_clk = ~mul_ref_clk;
         end 
        end 
   end 
 end 
 endgenerate 
       assign multiply_clk = mul_ref_clk;

Upvotes: -2

Views: 131

Answers (1)

Mikef
Mikef

Reputation: 2508

Generate statements are evaluated during elaboration which occurs before t = 0 in a simulation. Therefore normal variables (updated dynamically as the RTL runs) can't be used a arguments to generate statements.

Elaboration from 1800 2012 section 3:
Elaboration occurs after parsing the source code and before simulation; and it involves expanding instantiations, computing parameter values, resolving hierarchical names, establishing net connectivity and in general preparing the design for simulation.

Generate statements from IEEE 1800 2012 section 27:
Generate schemes are evaluated during elaboration of the design. Although generate schemes use syntax that is similar to behavioral statements, it is important to recognize that they do not execute at simulation time. They are evaluated at elaboration time, and the result is determined before simulation begins. Therefore, all expressions in generate schemes shall be constant expressions, deterministic at elaboration time. For more details on elaboration, see 3.12

Upvotes: 2

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