CODEWITHSUNDEEP
verilogsystem-verilog
peter
peter

Reputation: 107

Verify system verilog parameter during compile/elab time

I am trying to validate a parameter inside a verilog module as follows:

module ram #(
    parameter WIDTH   = 16    
) (
    input wire clk,
    input wire reset,
    input wire load,
    ...
);


  if ((WIDTH   == 0)) begin
    $error(
        "WIDTH   cannot be zero"
    );
  end

  endmodule

when WIDTH is invalid, other parts of the module can give errors as well. For example:

reg [WIDTH-1: 0] mem;

would give an error when WIDTH is zero.

In such a case, elaboration stage emits error related to above, possibly because it encounters that error before my validity check. Is there a way to force parameter validation code to be elaborated first so it will emit "WIDTH cannot be zero" before others?

Upvotes: 0

Views: 513

Answers (1)

dave_59
dave_59

Reputation: 42623

There is no way to control when elaboration evaluates conditional generate expressions. In fact they are probably evaluated as late as possible so you could write things like

if ($bits(mem) < 2) begin
  $error(
      "mem WIDTH cannot be less than 2"
  );
end

You could write your code to avoid the other errors

logic [(WIDTH? WIDTH-1:0): 0] mem;

But that seems like a lot of work to avoid the extra error messages.

Upvotes: 2

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