CODEWITHSUNDEEP
cpu-architectureendiannessriscvinstruction-encoding
WooLyung
WooLyung

Reputation: 1

Little Endian in Instruction

I'm learning about RISC-V instructions in Computer Architecture. What i wonder is, because of little endian, any number in RISC-V's instruction's little digit is on little bit. I know that RISC-V use little endian to express data in memory. but I'm not sure it is same to express number in instructions.

for example, add instruction has that form, [funct7][rs2][rs1][funct3][rd][opcode], MSB is in funct7, LSB is in opcode. and rs1, rs2, rd is some number with 5bits. if [rd] is 0b00001, position of 1 is LSB in rd's 5 bits. this point is my question. is reason that 1's position is LSB, RISC-V use little endian? if that is right, is (0b00001's) position of 1, MSB in big endian?

Upvotes: 0

Views: 1044

Answers (1)

Erik Eidt
Erik Eidt

Reputation: 26646

No, endian-ness only changes byte order, not bit ordering within fields of instructions.  In fact, we cannot observe the complete "bit ordering" because the individual bits don't have their own addresses (but we can see the effects of byte ordering when a field crosses a byte boundary).

It is true that the order of the fields themselves in RISC V are sort-of reversed from (big endian) MIPS, but that is really only so that the opcode field comes in the first byte — the lowest address of the bytes in the instruction.  This allows for variable length instructions, with little endian memory.  The lowest bits of the opcode determine the instruction length.

Upvotes: 1

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