CODEWITHSUNDEEP
vhdlvivadodigital-logic
Eve
Eve

Reputation: 1

width mismatch in assignment; target has 10 bits, source has 8 bits error

I try to write VHDL code in Vivado to show multiply 8 bit number by 1,2,3,4. i got the error in line (y <= ..) : " width mismatch in assignment; target has 10 bits, source has 8 bits error in vhdl" i dont understand whats the problem

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std;
use IEEE.STD_LOGIC_unsigned.ALL;



entity multiplies is
    Port ( sel : in STD_LOGIC_vector (1 downto 0);
           x : in STD_LOGIC_VECTOR (7 downto 0);
           y : out STD_LOGIC_VECTOR (9 downto 0));
end multiplies;

architecture Behavioral of multiplies is

component multi
port (i0: in std_logic_vector(9 downto 0);
      X : in std_logic_vector(9 downto 0);
      z: in std_logic_vector(9 downto 0));
END COMPONENT;

signal A2: std_logic_vector(9 downto 0); 
signal A3: std_logic_vector(9 downto 0);
signal A4: std_logic_vector(9 downto 0);

begin

with sel select

Y<= (x) when "00",
    A2 when  "01",
    A3 when "10",
    A4 when others;
  
end Behavioral;

Upvotes: 0

Views: 894

Answers (1)

TonyM
TonyM

Reputation: 124

Port x is 7:0 whereas port y is 9:0.

So you can't assign x to y directly in your with-select clause, you correctly get an error.

That part of the clause can instead be:

Y  <=  "00" & x  when "00",
       A2        when "01",
       A3        when "10",
       A4        when others;

Upvotes: 1

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