CODEWITHSUNDEEP
fpgavivado
sali
sali

Reputation: 1

I got pin planning errors while generating bitstream, what is the problem here?

While generating bitstream I get following errors:

[DRC NSTD-1] Unspecified I/O Standard: 9 out of 14 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: out[7:0], and reset.

[DRC UCIO-1] Unconstrained Logical Port: 9 out of 14 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: out[7:0], and reset.

Upvotes: 0

Views: 2389

Answers (1)

Mikef
Mikef

Reputation: 2510

This error occurs during implementation (aka place & route) when a design is targeted to a device which has physical package pins, however the package pin numbers are not specified by the user.
Same with the IO standard (TTL/CMOS) etc.

The tool is saying the user (oversimplified by me for understanding):
'You have NOT told the tool what package pins to use'

There is no expectation of hardware behaving in a designed way without specifying the pin numbers.

As stated at the link below:
"The error message is to notify customers that they need to set IOSTANDARD and PACKAGE_PIN, in order to protect devices from accidental damage that could be caused by the tools randomly choosing a pin location or IOSTANDARD without knowledge of the board voltage or connections.

For example: If a pin is tied to ground on a board and Vivado chooses this pin as an output that is driving high, this causes contention.

If you have a termination scheme on the board for a pin that is the HSTL or SSTL recommended termination, and Vivado chooses LVCMOS18 (default), the signal integrity of the signal will be less than optimal"

This link supplies different ways out of the error based on what you are trying to do (including fixing the error by providing pin numbers and IO standards).
https://support.xilinx.com/s/article/56354?language=en_US

For this to operate on hardware, the top_module port/pins/io list need to assigned to specific pins on the physical part.

The exact solution also depends on if the user is using the Vivado GUI (project mode) or using a tcl (script/non-project) flow.

This Xilinx tutorial helpful also for pin planning. See lab 1, step 5
https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2022_2/ug888-vivado-design-flows-overview-tutorial.pdf

Physical package pin numbers are not specified using RTL languages (like Verilog & VHDL). They are specified in the device vendors GUI, or in a separate file, often .tcl or .sdc, or .xdc.

The jargon used around this topic could be confusing. The term package pin could also be referred to as pad, location, or just loc in documentation and tools.

Upvotes: 1

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