CODEWITHSUNDEEP
binaryvhdlfpgadivisionlattice-diamond
Keith Beech Hall
Keith Beech Hall

Reputation: 1

(VHDL-1154) near 'std_logic_vector' ; type conversion expects one single argument

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.ALL;
use ieee.math_real.all;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;

port 
(
    
    signal Led_7                :   out std_logic := '1';
    signal Led_6                :   out std_logic := '1';
    signal Led_5                :   out std_logic := '0';
    signal Led_4                :   out std_logic := '0';
    signal Led_3                :   out std_logic := '0';
    signal Led_2                :   out std_logic := '0';
    signal Led_1                :   out std_logic := '0';
    signal Led_0                :   out std_logic := '0';
    signal Binary8bitLED                :   out std_logic_vector(7 downto 0) := "00000000"

);

architecture rtl of i2s_interface_1 is

signal Binary8bitData               :   std_logic_vector(7 downto 0) := "10010110";
signal Binary8bitdivider            :   std_logic_vector(7 downto 0) := "00001010";

begin
        prescaler: process(clk)     
    begin

    Binary8bitLED   <= std_logic_vector((to_signed(to_integer(to_signed(Binary8bitData)) /                    (to_integer(to_signed(Binary8bitdivider))))),8);



    Led_7 <= '1';
    Led_6 <= '1';
    Led_5 <= '1';
    Led_4 <= '1';
    Led_3 <= '1';
    Led_2 <= '1';
    Led_1 <= '1';
    Led_0 <= '1';
    
    -- Binary8bitLED Output here

    end process;
end architecture;

The code is a snippet of the relevant bits. I want to divide (Binary8bitData / Binary8bitdivider) to get a remainder of 15 so "00001111" - > Binary8bitLED

convert the remainder into the LED's on my FPGA.

its a test code to divide binary numbers and I'm looking to show the answer through 8 LED's.

10010110 / 1010 = 15 r 0.

Upvotes: 0

Views: 204

Answers (1)

Tricky
Tricky

Reputation: 4471

to_signed(Binary8bitData) cannot find an appropriate function, as slv to signed conversion can be done by a simple type conversion rather than a conversion function:

signed(Binary8bitData)

But you have a further issue: You have included the non-standard synopsys std_logic_arith package. This has duplicate definitions of signed and unsigned types defined in the VHDL standard numeric_std package. This means the compiler does not know which version of to_signed or signed type you want, and hence all will be invisible. You should delete the line:

use ieee.std_logic_arith.ALL;

from your code.

Upvotes: 2

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