CODEWITHSUNDEEP
simulationsystem-verilogverification
Gus Mantzorogeorge
Gus Mantzorogeorge

Reputation: 13

How does a covergroup handle with an event handle sampling when enabling strobe?

I am curious as to how the sampling happens in a SystemVerilog covergroup when we have an event specified and we also use type_option.strobe = 1 for said covergroup. For example:

covergroup c @(posedge clk)
 type_option.strobe=1;

strobe implies sampling happens in the Postponed region, however the @(posedge clk) as an event is evaluated at the Active region. How does the sampling function resolve this?

I tried reading the LRM, but it wasn't very cohesive.

Upvotes: 1

Views: 175

Answers (2)

dave_59
dave_59

Reputation: 42738

When type_option.strobe = 0, the default, sampling occurs immediately in whatever region the sampling event gets triggered. In some odd cases, that could mean sampling multiple times within the same time slot.

When type_option.strobe = 1, the sampling event just schedules the actual covergroup sampling to occur once in the postponed region.

Upvotes: 1

toolic
toolic

Reputation: 62227

From IEEE Std 1800-2017, Table 19-3—Coverage group type (static) options:

strobe=boolean

When true, all samples happen at the end of the time slot, like the $strobe system task.

Also, section 4.4.2.9 Postponed events region:

$monitor, $strobe, and other similar events are scheduled in the Postponed region.

Therefore, setting strobe=1 forces the sampling to occur in the Postponed region. If strobe=0, sampling is not forced into the Postponed region.

Upvotes: 0

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