ModelSim has inconsistent output. Is this a bug?

Question

I noticed that suddenly a signal in my testbench turned x.

I tried to find the cause and according to the verilog, the signal should ever be only either z or 0. Since sda_padoen_o is 0, sda should be sda_pad_o which should always be 0. Somehow sda is x nonetheless.

Is there a flaw in my conclusion or did I find a bug in modelsim?

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inout wire sda
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assign sda = sda_padoen_o ? 1'bz : sda_pad_o;
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i2c_master_byte_ctrl byte_controller (… .sda_o(sda_pad_o), …);

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output wire sda_o;
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i2c_master_bit_ctrl bit_controller (… .sda_o(sda_o), …);

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output wire sda_o;
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assign sda_o = 1'b0;